基于DDR2存储器的FIFO设计

Design of FIFO based on DDR2 SDRAM

针对许多应用系统对FIFO深度不断增长的需求与SRAM技术较低的存储密度之间的矛盾,提出了设计一套使用DDR2存储器,且在FPGA上实现FIFO访问控制的解决方案。设计了一个具有较低访问延迟的DDR2控制器自行实现DDR2存储器所需的自刷新、访存调度、地址译码等操作,通过并发访问和时钟同步,提供了与典型同步FIFO存储器兼容的访问接口。重点研究DDR2标准中用于支持并行访问和信号传输的若干特性,并给出了一种低访问延迟的DDR2控制器状态机表示。所设计的FIFO接口能够支持并行数据读写,具有固定的访问周期。研究和测试结果表明,FIFO接口完全屏蔽了DDR2复杂的内部时序,能提供较高的访问速率,且深度可配置。

Aiming at the growing demand of FIFO depth and the lower storage density of SRAM technology in many applications, a FIFO access control solution for DDR2 in FPGA was proposed. The scheme was composed by a DDR2 controller with lower access latency, to achieve self-refresh, memory access scheduling, address decoding and other operations, and an access interface compatible with typical synchronous FIFO memories. Some special feature on DDR2 specification was focused on, and a DDR2 controller state machine with low-access latency was given. The FIFO interface was designed to support parallel data reading and writing in a fixed access cycle. The testing results indicate that the FIFO interface has a high access rate, and the depth of the FIFO system can be configured.