一种雷达信号处理芯片的8B/10B编码电路设计

Design of 8B/10B Encoding Circuit for Radar Signal Processing Chip

为满足某雷达信号处理芯片与系统中其他功能单元的高速互联,在芯片中专门设计了Ser-Des接口模块,并对其核心部件8B/10B编码器进行了重点设计和Verilog实现[1]。根据8B/10B编码理论对编码电路进行模块划分和逻辑优化,尤其是将数据字符编码模块d-code划分为5B/6B、3B/4B编码查找表和逻辑输出模块。其中查找表进行简单的数据映射,逻辑输出模块通过特定函数实现极性转换和组合输出。基于该方案的8B/10B编码器结构简单、逻辑清晰、资源占用率少,并且可以作为IP核实现重复利用。

In order to achieve high speed intercommunication between a radar signal processing chip and other functional units, a SerDes interface module is specially designed in the chip. The core of 8B/lOB encoder is de- signed and Verilog implementation^l! is provided. Based on 8B/lOB encoding theory, module partition and logic optimization to the encoding circuit is performed, especially the data character encoding module d code is parti- tioned into 5B/6B, 3B/4B code look-up table （LUT） and logic output modules. The method of LUT is used ibr simple data mapping, polarization conversion and combination output is achieved by the logic output module through specified function. The 8B/10B encoder based on this scheme has many merits, such as simple structure, clear logic and taking less resource, moreover this 8B/lOB encoder can be used as IP core repeatedly.