电力线载波通信定时同步算法及其FPGA实现

Power line carrier communications timing synchronization and FPGA implementation

基于电力线载波通信G3技术标准下的物理层协议,针对电力线上噪声干扰较大,造成帧同步有虚警现象,符号定时同步尖峰幅值随信号衰减变化以及尖峰的旁瓣超过门限等缺点,提出了准确性更高、占用硬件资源相对较少的电力线载波通信帧同步与符号定时算法。通过算法仿真,表明该算法在信噪比较低时,具有门限自适应性,能够克服旁瓣的干扰,并易于硬件实现的特点。在一发一收两块现场可编程门阵列(FPGA)开发板上验证,提出新的帧同步、符号定时算法和硬件实现方案,实现了对电力线载波通信的正交频分复用(OFDM)基带系统进行实时、连续、准确的定时同步。

Large power line noise results in false frame synchronization and such problems as the peak amplitude in symbol timing synchronization changes with the attenuate signal and peak sidelobe exceeds the threshold.Therefore,based on the PLC G3 physical layer specification,this paper elaborated an improved frame synchronization and symbol timing synchronization algorithm with higher accuracy and less hardware resources occupancy.Through the simulation,the new algorithm shows adaptive threshold and better performance in conquering the interference of side lobe at low Signal-to-Noise（SNR）.And it is easier to design in hardware.In the end,in two development tools of which one sends out signal and the other receives signal validate even when there is a large power line noise,the method can still achieve accurate real-time,continuous timing synchronization on the power line carrier communication baseband system.