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考虑寄生参数的集成电路ESD损伤仿真方法 被引量：2

ESD damage simulation of integrated circuits by the consideration on parasitic parameters
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摘要 在传统的基于设计电路的ESD(Electro-Static Discharge)损伤仿真中,通常不考虑版图物理结构的影响,其仿真结果往往与实际损伤情况出现较大偏差,因此提出了一种考虑版图设计中寄生参数的集成电路ESD损伤的仿真方法.首先给出了仿真应用的具体分析流程.然后按照经验公式提取法明确了各种寄生参数的计算模型.最后,以集成运算放大器LM741为例,对其进行了ESD损伤模拟,再通过击打实验、失效定位与电性能测试,结果表明:仿真与实验结果具有较好的一致性,验证了该方法的有效性. In the traditional electro-static discharge （ESD） damage simulation based on logic circuit, the influence of layout was not taken into account as usual, and there was larger deviation between the results of simulation and the actual damage, so a new simulation method of ESD damage for integrated circuits was presented by the consideration for parasitic parameters extraction in layout. Firstly the specific simulation process in the application was given. Then the models of kinds of parasitic were defined according to empirical parameter extraction method. Lastly the ESD damage simulation for integrated operational amplifier LM741 as case study was carried out. According to zap test, failure location and electrical performance testing, the results showed have much consistency in simulation and experiment, and the validity of the simulation method is finally verified.
作者 吕卫民 胡冬 马静华 谢劲松
机构地区 北京航空航天大学可靠性与系统工程学院
出处 《北京航空航天大学学报》 EI CAS CSCD 北大核心 2011年第9期1100-1104,共5页 Journal of Beijing University of Aeronautics and Astronautics
基金 总装预研基金资助项目(9140A27020210JB1404)
关键词 ESD损伤 版图结构 寄生参数 电路仿真 可靠性设计 ESD damage layout parasitic parameter circuit simulation design for reliability
分类号 TN406 [电子电信—微电子学与固体电子学]
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参考文献15

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同被引文献20

  • 1王勇,李兴鸿.深亚微米集成电路中的ESD保护问题[J].电子与封装,2005,5(10):26-31. 被引量：2
  • 2黄庆敏,罗键.HDMI接口标准及应用设计[J].电视技术,2007,31(2):32-34. 被引量：21
  • 3SMEDES T, TRIVEDI N, FLEURIMONT J, et al. A DRC-based check tool for ESD layout verification [ C ] // Proceedings of the 31^st EOS/ESD Symposium. Anaheim, CA, USA, 2009:1 -9.
  • 4MITRA S, GAUTHIER R, SALMAN A, et al. I/O architecture for improved ESD protection in deep sub- micron SOI technologies [ C ] //Proceedings of 2006 IEEE International SOI Conference. Niagara Falls, NY, USA, 2006: 37-38.
  • 5MERGENS M P J, MARICHAL O, THIJS S, et al. Advanced SCR ESD protection circuits for CMOS/SOI nanotechnologies [ C ] // Proceedings of IEEE 2005 Custom Integrated Circuits Conference. San Jose, CA, USA, 2005:481-488.
  • 6CHEN T Y, KER M D. Analysis on the dependence of layout parameters on ESD Robustness of CMOS devices for manufacturing in deep-Submicron CMOS process [ J ]. IEEE Transactions on Semiconductor Manufactu ring, 2003, 16 (3): 486-500.
  • 7Mentor Graphics Corporation. Calibre xRC parasitic ex- traction [EB/OL] . (2012 - 08) [2013 - 04] http: //www, mentor, com/products/ic_ nanometer_ de- sign/verification-signoff/eircuit-verifieation/ealibre-xrc/.
  • 8CHEN T Y, KER M D, WU C Y. The application of transmission-line-pulsing technique on electrostatic dis- charge protection devices [ C ] //Proceedings of 1999 Taiwan EMC Conference. Taipei, China, 1999: 260- 265.
  • 9周智勇.用于确保信号完整性的ESD保护器件新结构[J].电子产品世界,2009,16(12):58-60. 被引量：1
  • 10刘素玲,段平光,李霞,闫国英.静电放电模拟器电路建模分析[J].电波科学学报,2009,24(6):1172-1178. 被引量：8

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北京航空航天大学学报
2011年 第9期

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