任意阶LMSTDE算法的FPGA结构化设计

Structural design of arbitrary order LMSTDE algorithm in FPGA

提出了一种任意阶基于最小均方误差(LMS)自适应时延估计(LMSTDE)算法的现场可编程逻辑门阵列(FPGA)结构化设计方法.将原有的低阶次LMSTDE算法中速度受限的顺序迭代运算优化为只包含误差更新和权系数更新操作的全并行乘/加运算,并进一步分离为不依赖于阶次变量的功能运算单元,最后将软件设计中的结构化方法运用到FPGA的硬件设计中,实现了FPGA资源约束内的任意阶次全并行LMSTDE算法.仿真与性能验证表明:采用结构化设计方法实现的全并行LMSTDE算法提高了时延运算速度,在阶次上易于伸缩,并未改变原算法的误差收敛特性.

Method for optimized design and structured implement of arbitrary order LMSTDE （least mean square adaptive time delay estimate） algorithm in field programmable gate array （FPGA） was proposed. Time limited sequential iterative operation was optimized as parallel multiplicative and addi- tive operations, which realized updating error and updating coefficients. Then the existing LMSTDE algorithm was separated into operation units, which was independent of filter order variable. Lastly, by importing structural design method, which existed in software design, into FPGA, the arbitrary order LMSTDE algorithm was realized within the scope of FPGA recourses. Simulation and perform- ance experiment indicate that the parallel LMSTDE algorithm realized by structural design in FPGA increases operation speed and has flexible orders, and the definite anti-noise jamming performance is get without changing original algorithmrs convergence errors.