基于边界扫描技术的SOC数字电路可测性设计

Design for Testability of Digital Circuit in SOC Based on Boundary-Scan

随着SOC系统的快速发展,如何对其进行有效的测试与诊断是当前研究的热点问题。从SOC数字电路可测试性设计的角度出发,基于边界扫描技术,设计了具有边界扫描结构的IP核,并对相应的测试方法进行了研究。通过仿真及时序分析,验证了该设计方法的可行性,为SOC系统的测试提供了新的思路。

With rapid development of SOC,its test and diagnosis is becoming a research subject of interest.From the viewpoint of design-for-testability of digital circuits in SOC,an IP core with boundary-scan architecture was designed and corresponding test strategies were studied.Feasibility of the design methodology was validated by simulation and experimental results,which provided a novel approach for SOC test.