一种新颖的FPGA逻辑故障测试定位方法

A Novel Approach to Fault Testing and Diagnosis of FPGA

FPGA的生产测试是FPGA设计中非常重要的环节,不仅要求能够检测芯片是否发生故障,还必须进行精确的故障定位,以便设计人员对设计故障和工艺故障进行改进。依靠将CLB输出级联的方式进行故障定位,往往使测试激励在时序设计上变得更加复杂。灵活利用CLB周围的三态门资源,可以对FPGA逻辑故障进行快速准确的定位,且测试激励简洁。

Testing of FPGA plays an important part in FPGA design,which should not only detect fault on the chip but also locate it precisely,so that designers and process engineers could make improvement on it.Locating faults only by cascading outputs of CLB makes timing design in test bench more complicated.By using TBUF（three-state buffer） around CLB in a flexible way,logic faults in FPGA could be located more easily and more exactly with more compact test bench.