芯片层次化物理设计中的时序预算及时序收敛

Timing Budgeting and Timing Closure in Hierarchical Physical Design for ASICs

在深亚微米阶段,层次化物理设计已经成为主流,时序收敛受到越来越大的挑战。随着工艺的进步,线延时已成为时序收敛的关键。若在时序预算阶段不考虑物理信息,将会给项目带来极大风险。针对深亚微米芯片的物理设计特点,充分考虑各种物理因素对时序的影响,提出了一种物理感知时序预算、时序收敛方法。经过多款45nm、65nm工艺芯片的实践表明,该方法达到了时序快速收敛的目标。

This paper proposed a method of physical-aware timing budgeting and timing closure for hierarchical physical design of deep sub-micron ASICs.Timing closure is one of the biggest challenges in physical design,and the wire delay is a key point in timing closure.This method considered multiple influencing factor which impact the timing budgeting and timing closure.It is already applied on several chips in 45nm and 65nm technology,it can help to achieve rapid timing closure.