一种13bit 40MS/s采样保持电路设计

Design of a 13 bit 40 MS/s sample-and-hold circuit

设计了一个用于13bit40MS/s流水线ADC中的采样保持电路。该电路采用电容翻转结构,主运算放大器采用增益提高型折叠式共源共栅结构,以满足高速和高精度的要求。为减小与输入信号相关的非线性失真以获得良好的线性度,采用栅压自举开关。采用电源电压为3.3V的TSMC0.18μm工艺对电路进行设计和仿真,仿真结果表明,在40MHz的采样频率下,采用保持电路的SNDR达到84.8dB,SFDR达到92dB。

A 13 bit 40 MS/s sample-and-hold circuit for the pipelined A/D converters is designed. Capacitor flip-around ar- chitecture and gain-boosting folded cascade operational transconductance amplifier are adopted to achieve high resolution and resolu- tion. In order to reduce the nonlinearity related to input signal, a bootstrapped switch is used. The S/H circuit is designed and simulated in TSMC＇s 0. 18 μm CMOS process at 3.3V supply voltage. Simulation results show that SNDR of 84.8dB and SFDR of 92 dB are achieved at 40 MHz sampling rate.