π-旋转LDPC码的高效并行编译码结构设计

Parallel encoding /decoding architecture for π-rotation LDPC codes

该文设计了一种π-旋转LDPC码并行编/译码电路结构。利用π-旋转LDPC码的规则化旋转结构,编码、译码电路实现了分组并行处理。在信息迭代过程中,利用校验矩阵的旋转结构,使用一种二维数组存储译码迭代信息,不需要地址索引、只需通过映射即可取出所需参与运算的变量/校验信息,实现了迭代信息的分散存储、映射提取。这种分组、旋转结构简化了节点间的信息传输复杂度。并行译码电路具有一定的通用性,可以在译码速度和硬件复杂度之间进行折衷。

We propose partial parallel encoding/decoding architectures for π-rotation LDPC codes based on the rotating structure of permutation matrices.Two-dimensional arrays are designed to store the iterative information;therefore the variable/check messages needed in iterations can be retrieved out by the mapping architectures.Those rotation architectures can also reduce the message transmission complexity,therefore increase the throughput of LDPC decoders.The decoding architectures are suitable for reprogrammable,and can achieve a good tradeoff between hardware complexity and decoding throughput.