一种可局部动态实时重构的演化硬件平台

An Efficient High-Speed Real-Time Partially Reconfigurable Platform for Evolvable Hardware

为实现演化硬件能随外部环境的变化而自适应地改变芯片内部硬件结构的功能,设计了一种基于可编程片上系统的演化硬件平台。首先,该平台克服了商用FPGA的重构系统对演化硬件支持不足的问题,可以进行局部动态实时重构,且重构速度达到了1 600 Mbps。其次,该平台中的重构颗粒度可以灵活设计,避免了FPGA中重构粒度太细,电路染色体长度过长引起演化算法搜索时间过久的问题。最后,在EP2C50芯片上实现了该平台,并利用改进的遗传算法在该平台上进行了4种实际电路的演化实验。实验结果表明,规模为100的种群每演化一代的耗时约为0.07 s,验证了该平台进行硬件演化的有效性。

Aim. The introduction of the full paper reviews a number of relevant papers in the open literature, points out what we believe to be their shortcomings and then proposes what we believe to be an efficient partially reconfigurable platform design, which is explained in sections 1,2 and 3. Their core consists of： （ 1 ） we use the system on programmable chip （SOPC） to design the evolvable hardware platform which can enhance the reeonfiguration ability of commercial FPGA （field programmable gate array） and support high-speed real-time partial reconfiguration; the reconfiguration speed measured is 1600 Mbps; （2） the design of the reeonfiguration granularity of the evolvable hardware platform is flexible, thus overcoming the shortcomings that the reconfiguration granularity of commercial FPGA is too small and that the chromosomes of an evolvable circuit are too long and that the search time of the ge- netic algorithm is, too long; （3） we improve the existing genetic algorithm. With the improved genetic algorithm, section 4 implements our evolvable platform on Altera＇s EP2C50 FPGA chip and performs experiments on the evolution of four types of reconfigurable circuit; the experimental results, presented in Fig. 3, and their analysis show preliminarily that for a population size of 100, our evolvable hardware uses only about 0.07 seconds to evolve one generation of population, thus being efficient for circuit evolution.