基于FPGA的低密度奇偶校验码编码器设计

FPGA based design of LDPC encoder

为提高准循环低密度奇偶校验码(LDPC)编码过程中矩阵与向量乘法运算的运算速度,提高编码器的吞吐率,提出采用对数循环移位器实现这一运算的方案.设计了WIMAX标准中码率为1/2,码长为2 304的LDPC码的编码器.利用该码的校验基矩阵经过重组后可得到一个相邻的奇数行与偶数行非负元素所在的列号互不相同的矩阵的特点,在编码器的设计中充分利用了资源共享,采用6个对数循环移位器完成该码编码过程中的12组矩阵与向量乘法的并行运算.时序仿真和实际硬件测试的结果表明:与其他方法相比,该方案有效地降低了系统资源消耗,提高了吞吐率.

A logarithmic cyclic shifter based scheme was proposed to improve the operation speed of matrix-vector multiplication in the quasi-cyclic low density parity-check code（QC LDPC） encoding process and then improve the throughput of the encoder.An encoder was designed for an LDPC code defined in the WIMAX standard with a code rate of 1/2 and a code length of 2 304.The advantage of resource sharing was fully taken according to the characteristics of the base parity-check matrix which could be converted to a matrix with no two nonnegative elements in the same column in any two adjacent rows by row permutation.Six logarithmic cyclic shifters were used for the parallel calculation of twelve matrix-vector multiplications in the encoding process.Timing simulation and hardware test results show that the proposed solution reduces the resource consumed and improves the throughput effectively compared to other methods.