摘要
本系统采用CPLD和AVR单片机作为逻辑控制核心,设计了姿态存储测试系统,以实现姿态信息的采集、编帧和存储。详细介绍了姿态测试系统的工作原理和硬件设计。利用AVR单片机,控制数据的写、读、擦除操作,利用CPLD的逻辑控制功能完善了存储测试系统的各个工作状态,提高了存储测试系统工作的可靠性。验证了该系统可以完成对模拟信号的高速采样和存储。结合CPLD、AVR单片机和Flash存储器的优点,实现了8通道数据的高速采集,其存储容量大、噪声小、功耗低。
The system uses the CPLD and the AVR microcontroller as a logic control core and memory test system designed posture in order to achieve collection,code frame and storage of the attitude information.Described in detail the working principle and hardware design of the attitude test system.Using AVR microcontroller to control data write,read and erase operations,use the logic control functions of CPLD to improved storage test system of the working state.Improved the reliability of the work of the storage test system.Verify the system can completed high-speed sampling and storage for the analog signal.With the advantages of CPLD,AVR microcontroller and Flash memory to achieve high-speed 8-channel data collection,it has large storage capacity,small noise,low power consumption.
出处
《电子测试》
2011年第10期39-41,共3页
Electronic Test
