嵌入式系统芯片的软硬件协同仿真环境设计

Hardware/Software Co-verification Platform for Embedded Chip

针对嵌入式系统芯片SoC开发验证阶段的需求,介绍了一种通用的SoC软硬件协同仿真平台。软件仿真由C/C++和汇编语言编写,硬件仿真基于VMM验证方法学所搭建,SoC设计代码由RTL代码编写而成。将SoC设计代码中的ARM由DSM模型替代,通过VCS编译器将软硬件协同起来进行信息交互,实现一种速度快、真实性高、调试方便的通用性仿真平台。

With respect to the verification requirement of SoC design, an all purpose co verification platform is presented. Software simulation is written in C/C＋＋ and assembler language. Hardware simulation is based on VMM method. SoC code is written in RTL Verilog. ARM is substituted by DSM model. The simulation process executes communication through VCS. The simulation result verifies that the platform works well.