模糊控制器中高速除法器的FPGA设计

FPGA Design of High Speed Divider for Fuzzy Controller

为选择适用于FPGA硬件实现的模糊控制器中除法器的设计方案,分别采用LPM方法、不恢复余数移位减法和查找表法进行了设计和比较,给出了满足实时性和速度与资源平衡的设计方案。本设计基于Altera公司FPGA Cyclone II系列EP2C5Q208C7芯片,利用VHDL和Quartus II软件完成编译、仿真和下载和调试。该设计方法具有通用性,可生成IP核并适于高速运算场合。

In order to select proper divider design programme adaptting hardware realization for fuzzy controller with FPGA chip,use LPM,no-restoring remainder shift-subtraction and look-up table methods separately to complate design and making comparetion,confirming design programme satisfied with real-time and balance between rapidity and conservation.This design is based on the EP2C5Q208C7 chip of Cyclone II family produced by the Altera Company,using the VHDL programming language and the software of Quartus II to success compilation,simulation,download and debugging.The design method has advantage of commonality,can be created to be IP core and suitable for situation of high speed operation.