FIR滤波器的CSE优化算法设计及其FPGA实现

Optimal Common Subexpression Elimination Algorithm for FIR Filter and Implementation on FPGA

为了减少有限长单位冲激响应滤波器对FPGA资源的消耗,在水平共同子表达式消去算法和垂直共同子表达式消去算法的基础上,提出了一种优化CSE算法来设计滤波器,使滤波器运算单元得到更多的资源复用。应用DSP Bu ilder建立模型,以图形化界面实现一个32阶的低通有限长单位冲激响应滤波器,并用Modelsim和QuartusⅡ进行仿真。仿真结果表明:运用优化CSE算法设计的有限长单位冲激响应滤波器比用传统CSE算法设计的滤波器使用更少的逻辑单元,且优化设计的有限长单位冲激响应滤波器较直接乘法实现方式及分布式实现方式节省较多的硬件资源。最后,在A ltera公司DE2开发板上实现所设计的滤波器,硬件实现表明所设计的滤波器滤波效果和仿真结果一致。

To reduce the consumption of field programmable gate array resources,the horizontal common subexpression elimination algorithm and vertical common subexpression elimination algorithm in designing the FIR filter were studied.Further,an optimal common subexpression elimination algorithm combined the advantages of these two algorithms was presented in this paper so that the operation units can be reduced more efficiently.This paper built a model by using DSP builder firstly to implement a 32-order low-pass FIR filter and then simulated the model with Modelsim and QuartusⅡ.The simulation result shows that the optimal CSE design uses less logic elements and logic depths,and the optimization FIR filter design saves more hardware resources than the direct multiplication method and the distributed method do.Finally,the implementation of designed filter was done on DE2 development board.The result shows that the filtering effect is in keeping with the simulation result.