期刊文献+

一种多核Cache低功耗动态混合划分算法研究 被引量:2

Research on Low-power Dynamic Hybrid Cache Partitioning for CMP
下载PDF
导出
摘要 随着片上集成核数的增多,片上Cache的面积也越来越大,同时消耗的能耗也越来越多.因此,面向低功耗的Cache划分方法不可避免地成为了Cache划分中需要考虑的一个重点.然而,目前的Cache划分算法主要是面向公平性、性能或者QoS的,很少考虑到功耗问题.面向低功耗的混合划分方法(LPHP)利用程序运行的局部性原理,将在L2 Cache中访问差异度较大的线程作为一个划分单位,通过私有和共享两种资源分配方式相结合来实施Cache划分,从而实现在运行同一个应用时,使用更少的Cache列,关闭剩余列,达到降低系统功耗的目的.LPHP通过减少在使用的Cache列来达到降低功耗的目的,符合当前多核发展低功耗的趋势. As the number of cores on CMP increases, the size of an on-chip cache increases and it consumes more and more power of the whole system. So low-power oriented design has become an inevitable trend. However currently most of the partitioning strategies are aimed at throughput or fairness, ignore the power consumption. In order to reduce system power consumption, a new low-poweroriented hybrid partitioning (LPHP) strategy for shared cache is proposed in this paper. Due to the program loeaiity principle, it uses both private and shared resource-allocation methods to implement the partitioning strategy by combining the two threads whose access appears large difference into one partitioning unit at run-time. Then when running the same application, some of the cache columns can be closed within the performance degradation threshold (PDT).
作者 方娟 杜文娟
出处 《小型微型计算机系统》 CSCD 北大核心 2011年第11期2295-2298,共4页 Journal of Chinese Computer Systems
基金 国家自然科学基金项目(60873145)资助 国家"九七三"重点基础研究发展计划基金项目(2007CD311100)资助
关键词 低功耗 动态划分 共享CACHE 片上多核 low power dynamic partition shared cache chip multi-processor
  • 相关文献

参考文献11

  • 1Sinharoy B, Kalla R N, Tender J M, et al. Power 5 system micro- architecture [J]. IBM J. Res. Dev, 2005, 49(4/5) :505-521.
  • 2McNairy C,Soltis D. Itanium 2 processor micro architecture [J]. IEEE Micro, 2003,23(02) :44-55.
  • 3熊伟,殷建平,所光,赵志恒.多核处理器面向低功耗的共享Cache划分方案[J].计算机工程与科学,2010,32(10):26-29. 被引量:2
  • 4Chang J. Cooperative caching for chip multi-processors [ D]. Madison, Wisconsin, USA: University of Wisconsin at Madison, 2007 : 385 -396.
  • 5Liu C, Sivasubramarfiam A, Kandemir M. Organizing the last Line of defense before hitting the memory wall for CMPs[ C]. Proceed- ings of the 10th International Symposium on High Performance Computer Architecture ,2004:176-185.
  • 6Lin J, Lu Q, Ding X, et al. Gaining insights into multi-core cache partitioning: bridging the gap between simulation and real systems [ C]. Proe. of the 14th Int Syrup on High-performance Computer Architecture ( HPCA 14). Salt Lake City, Utah: IEEE, 2008: 367-378.
  • 7Matick R E,HeUer A M I T J. Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hier- archy using miss rates and queuing theory [J]. IBM Journal Of Research And Development,2001,45 (6) :819-843.
  • 8Christensson M, Eskilson J, et al. Simies:a full system simulation platform [ J]. IEEE Computer,2002,35 (2) :50-58.
  • 9Qureshi M K, Part Y N. Utility based cache partitioning: a low o- verhead, high performance, nmtime mechanism to partition shared caches [ C ]. Proc. of the 3901 Annual IEEE,/ACM Int Symp on Microarchitecture. Orlando, Florida, USA: IEEE,2006:423 -432.
  • 10Kim S, Chandra D, Solihin Y. Fair cache sharing and partitioning in a chip multiprocessor architectuer [ C]. Proc. of PACt 2004. Antibes, Juanles-Pins, France:IEEE, 2004:111-122.

二级参考文献16

  • 1Suh G E,Devadas S, Rudolph L. A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning[C]//Proc of the 18th Int'l Symp on High-Performance Computer Architecture, 2002 : 117-128.
  • 2Suh G E, Rudolph L, Devadas S. Dynamic Partitioning of Shared Cache Memory[J]. Journal of Supercomput, 2004,28 (1): 7-26.
  • 3Dybdahl H, Stemtr P, Natvig L A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors[C]//Proc of the 13th Int'l Conf on High Performance Computing,2006:22-34.
  • 4Qureshi M K,Patt Y N. Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches[C]//Proc of IEEE/ACM Int'l Syrnp on Microarchitecture, 2006 : 423-432.
  • 5Suo Guang, Yang Xuejun, Liu Guanghui, et. al. IPC-Based Cache Partitioning: An IPC-Oriented Dynamic Shared Cache Partitioning Mechanism[C]//Proc of ICHIT' 08, 2008 : 399- 406.
  • 6Mattson R L, Geesei J,Slutz D R, et al. Evaluation Techniques in Storage Hierarchies [J]. IBM System Journal, 1970,9(2): 78-117.
  • 7Matick R E,Heller T J,Ignatowski M. Analytical Analysis of Finite Cache Penalty and Cycles Per Instruction of a Multiprocessor Memory Hierarchy Using Miss Rates and Queuing Theory[J]. IBM Journal of Research And Development, 2001,45(6) :819-842.
  • 8Rajkumar R, Lee C, Lehoczky J, et al. A Resource Allocation Model for QoS Management [C]// Proc of the 18th IEEE Real-Time Systems Symp, 1997 : 298-307.
  • 9Ranganathan P, Adve S,Jouppi N P. Reconfigurable Caches and Their Application to Media Processing[C]//Proc of the 27th ISCA, 2000:214-224.
  • 10Reddy R,Petrov P. Eliminating Inter-Process Cache Interference Through Cache Reconfigurability for Real-Time and Low-Power Embedded Multi-Tasking Systems[C] //Proc of CASES' 07,2007 : 198-207.

共引文献1

同被引文献17

  • 1张勤勇,蒋洪川,刘翠华.分子动力学模拟的优化与并行研究[J].计算机应用研究,2005,22(8):84-85. 被引量:5
  • 2Qu G. What is the limit of energy saving by dynamic voltage scal- ing [C]. Proceedings of the 2001 ence on Computer-aided Design USA,2001:560-563. IEEE/ACM International Confer- ( ICCAD ) , San Jose, California,.
  • 3Pillal P,Shin K G. Real-time dynamic voltage sca/ing for low-pow- er embedded operating systems[ C ]. Proceedings of the ACM Sym- posium on Operating Systems Principles ( SOSP), Chateau Lake Louise, Banff,Canada,2001:89-102.
  • 4Kim W, Shin D, Yun H, et al. Performance comparison of dynamic voltage scaling algorithms for hard real-time systems[ C]. Proceed- ings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium ( RTAS ), San Jose, California, USA, 2002:219-228.
  • 5Chen J, Kuo C. Energy-efficient scheduling for real- time systems on dynamic voltage scaling (DVS) platform[ C]. In 13th IEEE In- ternational Conference on Embedded and Real-Time Computing Systems and Applications ( RTCSA), Daegu, Korea,2007 : 28 -38.
  • 6Gruian F, Kuchcinski K. Uncertainty-based scheduling: energy-effi- cient ordering for tasks with variable execution time [ C ]. Proceed- ings of the 2003 International Symposium on Low Power Electron- ics and Design (ISLPED) ,Seoul ,Korea,2003:465-468.
  • 7Swaminathan V, Chakrabarty K. Energy-conscious, deterministic I/ O device scheduling in hard real-time systems [ J ]. IEEE Transac- tions on Computer-Aided Design of Integrated Circuits and Sys- tems,2003,22 ( 7 ) : 847-858.
  • 8Fan X, Ellis C, Lebeck A. The synergy between power-aware mem- ory systems and processor voltage scaling [ C ]. In Workshop on Power-Aware Computing Systems,2003.
  • 9Snowdon D, Ruocco S, Heiser G. Power management and dynamic voltage scaling: myths and facts [ C ]. Proceexiings of the 2005 Workshop on Power Aware Realtime Computing, New Jersey, USA, 2005.
  • 10Jejurikar R, Gupta R. Dynamic voltage scaling for system-wide en- ergy minimization in real-time embedded systems [ C ]. Proceedingsof the 2004 International Symposium on Low Power Electronics and Design (ISLPED) ,Newport Beach ,California,USA,2004:78-91.

引证文献2

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部