高速曼码解码器及其I^2C接口的FPGA实现

FPGA implementation for a high-speed manchester decoder and its I^2C interface

针对测井系统中高波特率的数据传输要求,提出了1种曼彻斯特码解码器及其I2 C接口的FPGA实现方案,利用Altera Cyclone II系列的EP2C8T144C8N芯片完成硬件解码功能,以取代低波特率下的单片机软件解码,提高了系统传输速率和稳定性。文中具体讨论了该系统的解码电路、FIFO缓存,以及与后级处理器之间的I2 C接口在FPGA中的VHDL描述方法。着重分析了基于电平宽度检测的曼码解码原理和I2 C接口的单进程状态机设计思想。经过软件综合仿真及硬件电路调试,该解码系统可在大于12.5kBps的波特率下稳定可靠地工作。

As to the requirement of transmission with high baud rate on logging system,this paper puts forward an implementation of FPGA in the Manchester decoding system.This method will enhance the transmission rate of system after making improvement on the basis of the former logging system.This paper concretely discusses the FPGA implementation of the decoding circuit,FIFO buffer memory and I2C interface in the system.The Manchester decoding system on the basis of the width detection to voltage level and the designing idea of state machine with I2C interface are mainly introduced.After the hardware test,this decoding system can operate stably and reliably with a baud rate higher than 12.5 kBps.