摘要
A high performance quadrature voltage-controlled oscillator （QVCO） is presented. It has been fabricated in SMIC 0.18 μm CMOS technology with top thick metal. The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation. Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise. A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO. The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz, while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply. The QVCO can operate from 4.09 to 4.87 GHz （17.5%）. Measured tuning gain of the QVCO （Kvco） spans from 44.5 to 66.7 MHz/V. The chip area excluding the pads and ESD protection circuit is 0.41 mm2.
A high performance quadrature voltage-controlled oscillator （QVCO） is presented. It has been fabricated in SMIC 0.18 μm CMOS technology with top thick metal. The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation. Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise. A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO. The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz, while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply. The QVCO can operate from 4.09 to 4.87 GHz （17.5%）. Measured tuning gain of the QVCO （Kvco） spans from 44.5 to 66.7 MHz/V. The chip area excluding the pads and ESD protection circuit is 0.41 mm2.
基金
supported by the Ministry of Industry and Information Technology of China(No.2009ZX03006-009)
