一种H.264去块效应滤波器的硬件结构

An efficient hardware architecture for H.264 deblocking filter

为平衡边界处理中数据依赖关系与宏块滤波速度的矛盾,提出一种H.264去块滤波的硬件结构,48条边界按照一种有效的顺序流水线处理,2个像素样本行数据并行滤波计算;滤波计算过程分为5个阶段,各阶段之间采用流水线结构,很好地平衡了各个阶段的操作过程.在SMIC0.13μm CMOS工艺库下的综合结果表明,电路在300MHz的时钟频率下消耗12.33×103个逻辑门,对于分辨率为3 840×2 160的超高清视频,处理速度可以达到86帧/s,可以满足其实时编码需求.

A hardware architecture for H. 264 deblocking filter is proposed, in order to balance the conflict between the dependency relationship of adjacent data and the processing speed, the 48 edges are processed in pipeline with an effective order; the data from two pixel-lines are filtered in parallel. In addition, a 5-stage pipelined structure is employed by the filtering computation to balance the operation procedure of each stage. While working at eloek frequency of 300 MHz, synthesized under 0. 13 Ixm CMOS standard cell technology, the proposed architecture can process the picture of 3 840 × 2 160 with 86 frame/s, which easily meets the throughput requirements of real time coding, while consumes only 12. 33 × 103 gates.