串行总线合成仪器设计与实现

Design and realization of serial bus synthetic instrument

设计了1种VXI总线接口的串行总线合成仪器。该仪器以FPGA为核心,分别开发了符合1553B、ARINC 429和UART协议的软件核,根据测试需求可将上述软件核动态配置于1块C尺寸的VXI模块中,实现3种不同协议数据总线传输条件下的测试。根据不同总线的电平特点,设计了相应的接口适配电路,将FPGA的逻辑电平转换成总线电平,并具有隔离和驱动能力。所有收、发的数据都缓存在FPGA内的FIFO中,通过VXI总线接口完成串行总线与上位机的实时数据通信。实验结果表明,本文设计的合成仪器能够满足3种串行总线通信协议的解析与合成,应用前景广阔。

A serial bus synthetic instrument with VXI bus interface is designed in this paper. This instrument takes FPGA as core. Three different software cores are developed according with 1553B, ARINC 429 and UART protocols. These software cores could be dynamically reconfigured in one VXI bus C-size module to test three buses of different protocols. The interface adaption circuit is designed to meet the level character of three buses. It transforms the logical level of FPGA to the corresponding bus level. The ability of isolation and driving are also included. All the data sent or received is saved in the FIFO of FPGA. It uses the 32 bits VXI bus to complete the data communication between the serial bus and the host computer. The experiment results show that the synthetic instrument designed by this paper can meet the interpretation and synthesis of three serial bus communication protocols, and has broad application prospect.