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一种提高阻变存储器擦除可靠性的写电路设计 被引量：4

A Novel RRAM Write Circuit with Improved Reset Reliability
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摘要 针对现有阻变存储器中严重影响擦除操作可靠性的"写回"现象,结合测试数据、材料特性及电路原理分析了引起这种现象的主要原因,给出了一种加入"擦除反馈"功能的写电路设计方案。该方案能够对擦除操作进行监控,一旦发现操作完成,立即使用反馈电路关闭写驱动的输出以停止擦除操作,防止"写回"现象。优化后的写电路方案在0.13μm标准CMOS工艺下进行了流片验证。通过测试数据的分析对比,可以看到相比传统的写电路方案,采用文中的电路设计能明显降低"写回失效"的可能,大幅度提高擦除操作的可靠性。 Aimed at the ＂set back＂ causing low reset reliability in current RRAM design,we demonstrated a novel solution based on the analysis of test data and circuit principles to overcome the issue.The solution introduces a function to detect the reset operation and uses a feedback circuit to close the write driver once the reset is finished,which can prevent the unexpected set back in reset operation.Our solution has also been validated under 0.13 μm CMOS logic process,and it is proved to be effective with the test data support that the reset reliability should improve a lot with feedback circuit.
作者 吴雨欣 李萌 林殷茵
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2011年第5期494-498,共5页 Research & Progress of SSE
基金 教育部光电技术及系统重点实验室资助课题(CETD00-09)
关键词 阻变存储器 写入与擦除 写驱动电路 比较与反馈 resistive memory set and reset write driver reedback
分类号 TN77 [电子电信—电路与系统] TN710 [电子电信—电路与系统]
  • 相关文献

参考文献6

  • 1Kawahara T, Takemura R, Miura K, et al. 2Mb SPRAM (SPin-Transfer Torque RAM) with bit-by- bit hi-directional current write and parallelizing-direc- tion current read[J]. Journal of Solid-state Circuits, 2008,43 (1) : 109-120.
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  • 6金钢,吴雨欣,张佶,黄晓辉,吴金刚,林殷茵.基于0.13m标准逻辑工艺的1Mb阻变存储器设计与实现[J].固体电子学研究与进展,2011,31(2):174-179. 被引量：4

二级参考文献8

  • 1Yang J J, Pickett M D, Li X M, et al. Memristive switching mechanism for metal/oxide/metal nanode- vices[J]. Nature Nanotechnology, 2008,160(3) :429- 433.
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共引文献3

同被引文献40

  • 1Wu Yi, Yu Shimeng, Guan Ximeng, et al. Recent progress of resistive switching random access memory [C], Silicon Nanoelectronics Workshop, 2012:1-4.
  • 2Li Hal, Chen Yiran. An overview of non-volatile memory technology and the implication for tools and architectures[C]. Design, Automation & Test in Eu- rope Conference & Exhibition, 2009:731-736.
  • 3Wang Meng, Luo Wenjiang, Wang Yenliang, et al. A novel cuxsiyo resistive memory in logic technology with excellent data retention and resistance distribution for embedded applications [ C]. VLSI Technology (VLSIT), 2010:89-90.
  • 4Tehrani S, Slaughter J M, DeHerrera M, et al. Mag- netoresistive random access memory using magnetic tunnel junctions[C]. Procedings of IEEE, 2003: 703- 714.
  • 5Xue Xiying, Jiang Wenxi, Yang Jianggen, et al. A 0. 13 tim 8 Mb logic based CuxSiyO resistive memory with self-adaptive yiled enhancement and operation power reduction[C]. VLSI Circuits (VLSIC), 2012: 42-43.
  • 6Lee Seung Ryul, Kim Young-Bae, Chang Man, et al. Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory[C]. VLSI Technology, 2012 : 71-72.
  • 7Higuchi K, Iwasaki T O, Takeuehi K. Investigation of verify programming methods to achieve 10 Million cycles for 50 nm HfO2 ReRAM[C]. IEEE Interna-tional Memory, 2010 : 107-112.
  • 8Wataru Otsuka, Koji Miyata, Makoto Kitagawa, et al. A 4 Mb conductive-bridge resistive memory with 2.3 GB/s read throughput and 216 MB/s program throughput[C]. IEEE Solid-state Circuits Conference, 2011:210-211.
  • 9Guido De Sandre, Luca Bettini. Phase change memory with 1.2 V 12 ns read access time and 1 MB/s write throughput[C]. IEEE Solid-state Circuits Conference, 2010:268-269.
  • 10SchrOgmeier P, Angerbauer M, Dietrich S, et al. Time discrete voltage sensing and iterative program- ming control for a 4F2 multilevel CBRAM[C]. VLSI Technology, 2007 : 186-187.

引证文献4

二级引证文献1

固体电子学研究与进展
2011年 第5期

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