期刊文献+

超大容量多级多平面分组交换结构聚集性研究

STUDY ON CLUSTERING PROPERTY OF SUPER-LARGE CAPABILITY MULTIPLEPLANE AND MULTIPLE-STAGE PACKET SWITCHING FABRIC
下载PDF
导出
摘要 研究超大容量MPMS结构聚集性问题,建立超大容量MPMS结构聚集性分析模型。给出MPMS结构顶点聚集集VGS、顶点聚集度VGD和顶点聚集系数VGC的精确定义,证明顶点聚集集、顶点聚集度和顶点聚集系数满足的3个定理。仿真结果证明了MPMS结构聚集性模型的正确性。 We studied in the paper the clustering property of the MPMS fabric with super-large capability, established the analysis model for clustering property of such MPMS, provided precise definitions of vertex gathering set ( VGS), vertex gathering degree (VGD) and vertex gathering coefficient ( VGC), all of the MPMS fabric, and proved three theorems which the VGS, VGD and VGC parameters met respectively. Simulation results showed the correctness of the proposed model.
出处 《计算机应用与软件》 CSCD 2011年第11期89-91,198,共4页 Computer Applications and Software
基金 国家自然科学基金项目(61003252)
关键词 交换结构 多级多平面 聚集性 MSMC结构 CBC结构 Switching fabric Multiple-plane and multiple-stage Clustering property MSMC fabric CBC fabric
  • 相关文献

参考文献7

  • 1Xiaohui Ye, Paul Mejia, Yawei Yin, et al. DOS-A scalable Optical Switch for Datacenters[C]//ACM/IEEE ANCS. October, 2010:46 - 51.
  • 2Chao-Yuan Jin, Kojima O, et al. Detailed Design and Characterization of All-Optical Switches Based on InAs/GaAs Quantum Dots in a Vertical Cavity[J]. IEEE Journal of Quantum Electronics,2010,46( 11 ) : 1582 - 1589.
  • 3Chao H J, Park J S, Artan S, et al. TrueWay: A highly scalable multi-plane multi-stage buffered packet switch [C]//Proc. IEEE HPSR. Hong Kong, May 2005:246 - 253.
  • 4Shen Y, Jiang S, Panwar S, et al. Byte-Focal: a practical load balanced switch[ C ]//Proc. IEEE HPSR. Hong Kong, May 2005:6 - 12.
  • 5马祥杰,李秀芹,兰巨龙,张百生.一种新型可扩展的多级多平面分组交换结构的图论模型与性能分析[J].电子与信息学报,2009,31(5):1026-1030. 被引量:4
  • 6Chuang S T, Mckeown N. Practical algorithm for performance guarantees in buffered crossbars [C]//IEEE INFOCOM. Florida, USA, 2005:981 - 991.
  • 7Cherry S. The Battle for Broadband (Internet protocol television) [J]. IEEE Spectrum, 2006,42 ( 1 ) :24 - 29.

二级参考文献8

  • 1Wang F, Zhu Wen-qi, and Hamdi M. The Central-stage buffered Clos-network to emulate an OQ switch[C]. IEEE Globecom Proceedings, California, USA, Nov. 2006: 4244-4257.
  • 2McKeown N. The iSLIP scheduling algorithm for input-queued switches[J]. IEEEIA CM Trans. on Networking, 1999, 7(2): 188-200.
  • 3Mekkittikul A and McKeown N. A practical scheduling algorithm for achieving 100% throughput in input-queued switches[C]. Proceeding of IEEE Infocom, San Francisco, USA, 2004: 792-799.
  • 4Clos C. A study of non-blocking switching networks[J]. Bell Systems Technical Journal, 1953, 32(1): 406-424.
  • 5Goke L R and Lipovski G J. Banyan networks for partitioning processor systems[C]. Proceeding Annual Symp Computer Architecture, USA, Dec. 2003: 21-28.
  • 6Wu C L and Feng T Y. On a class of multistage interconnection networks[J]. IEEE Trans. on Computers, 2000, 29(8): 694-702.
  • 7Pease M C. The indirect binary n-Cube microprocessor array[J]. IEEE Trans. on Computers, 2005, 26(5): 458-473.
  • 8Iyer S and McKeown N. Making parallel packet switches practical[C]. Proceeding of IEEE Infocom, USA, 2001, Vol.3: 1680-1687.

共引文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部