期刊文献+

面向特定应用的计算加速器虚拟化

Computation Accelerator Virtualization for Domain Specific Applications
下载PDF
导出
摘要 近年来,专用指令集处理器(application specific instruction set processor,ASIP)在嵌入式系统中得到了越来越广泛的应用.这些ASIP提供了面向某个领域定制硬件计算加速器的功能.通过利用加速器提供的扩展指令,可以大幅提升ASIP面向领域的处理能力.然而,这些计算加速器只能加速那些在编译时加入了扩展指令的应用程序.对于在编译时没有加入扩展指令的应用而言,得不到任何性能提升.利用软件动态二进制翻译来解决这一问题,即将计算加速器虚拟化.与传统的静态编译方法所不同的是,以动态虚拟化方式利用计算加速器面临许多新的问题.针对这些问题,提出了一系列解决方法,并用实验加以验证. In recent years, many embedded systems must meet the increasing demand of performing computation intensive tasks, such as video decoding, signal processing and so on. General purpose processors (GPPs), although inexpensive, may fail to meet the performance and power cost demands of embedded applications. Thus, it is increasingly common to use application specific instruction set processors (ASIPs) in embedded system designs. These ASIPs can customize hardware computation accelerators for an application domain. Along with instruction set extensions (ISEs), the customized accelerators can significantly improve the performance of embedded processors, which has already been exemplified in previous research work and industrial products. However, these accelerators in ASIPs can only accelerate the applications that are compiled with ISEs. Those applications compiled without ISEs can not benefit from the hardware accelerators at all. Software dynamic binary translation (DBT) is a technique typically used in virtual machines (VMs) to solve the binary compatibility problem and improve the performance. In this paper, we propose using software DBT to overcome this problem, i. e. computation accelerator virtulization. Unlike a static approach, dynamically utilizing accelerator poses many new problems. This paper comprehensively explores the techniques and design choices for dynamic accelerator utilization, and demonstrates the effectiveness by the experimental results.
出处 《计算机研究与发展》 EI CSCD 北大核心 2011年第11期2103-2110,共8页 Journal of Computer Research and Development
基金 国家"九七三"重点基础研究发展计划基金项目(2007CB310901) 国家自然科学基金项目(60773019 60803041)
关键词 计算加速器 动态二进制翻译 特定应用 虚拟化 专用指令集处理器 computation accelerator dynamic binary translation domain specific virtualization ASIPs
  • 相关文献

参考文献15

  • 1岳虹,沈立,戴葵,王志英.基于TTA的嵌入式ASIP设计[J].计算机研究与发展,2006,43(4):752-758. 被引量:9
  • 2Wu Q, Martonosi M, Clark D W, et al. A dynamic compilation framework for controlling microprocessor energy and performance [C] //Porc of Int Syrup on Microarchitecture. Washington, DC: IEEE Computer Society, 2005: 271-282.
  • 3Kiriansky V, Bruening D, Amarasinghe S. Secure execution via program shepherding [C] //Proc of the 11th USENIX Security Syrup, Berkeley, CA:USENIX, 2002:191-206.
  • 4Scott K, Davidson J. Safe virtual execution using software dynamic translation [C]//Proc of Annual Computer Seeurity Applications Conf. Washington, DC~ IEEE Computer Society, 2002:209-209.
  • 5Miller J E, Agarwal A. Software-based instruction caching for embedded processors[C]//Conf on Architectural Support for Programming Languages and Operating Systems. New York: ACM, 2006:293-302.
  • 6Pozzi L, Ienne P. Exploiting pipelining to relax register-file port constraints of instructionset extensions [C] //Proc of 2005 Int Con{ on Compilers, Architectures and Synthesis for Embedded Systems. New York: ACM, 2005:2-10.
  • 7Clark N, Blome J, Chu M, et al. An architecture framework for transparent instruction set customization in embedded processors [C]//Proe of the 32nd Annual Int Symp on Computer Architecture. New York: ACM, 2005:272-283.
  • 8Clark N, Kudlur M, Park H, et al. Application-specific processing on a general-purpose core via transparent instruction set customization [C] //Proc of the 37th Annual Int Symp on Microarchitecture. Washington, DC: IEEE Computer Society, 2004: 30-40.
  • 9Huynh H P, Sim J E, Mitra T. An efficient framework for dynamic reconfiguration of instruction-set customization [C] //Proc of the 2007 Int Conf on Compilers, Architecture, and Synthesis for Embedded Systems. New York: ACM, 2007: 135-144.
  • 10Bauer L, Shafique M, Kramer S, et al. RISPP: Rotating instruction set processing platform [C] //Proc of the 44th Annual Design Automation Conf. New York: ACM, 2007: 791-796.

二级参考文献10

  • 1K.Keutzer,S.Malik,A.R.Newton.From ASIC to ASIP:The next design discontinuity.In:Proc.IEEE Int'l Conf.Computer Design.Los Alamitos,CA:IEEE Computer Society Press,2002.84~90
  • 2Manoj Kumar Jain,M.Balakrishnan,Anshul Kumar.ASIP design methodologies:Survey and issues.In:Proc.14th Int'l Conf.VLSI Design.Los Alamitos,CA:IEEE Computer Society Press,2001.76~81
  • 3A.D.Gloria,P.Faraboschi.An evaluation system for application specific architectures.In:Proc.23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture.(Micro 23).New York:ACM Press,1990.80~89
  • 4N.Ghazal,R.Newton,Jan Rabaey.Retargetable estimation scheme for DSP architectnre selection.In:Proc.Asia and South Pacific Design Automation Conf.2000 (ASP-DAC 2000).New York:ACM Press,2000.485~489
  • 5Henk Corporaal.Transport triggered architectures:Design and evaluation:[Ph.D.dissertation].Netherlands:Delft Univ.of Technology,1995
  • 6Jan Hoogerbrugge.Code generation for transport triggered architectures:[Ph.D.dissertation].Netherlands:Delft Univ.of Technology,1996
  • 7Johannes A.A.J.Janssen.Compilation strategies for transport triggered architectures:[Ph.D.dissertation].Netherlands:Delft University of Technology,2001
  • 8R.G.Matthew,S.R.Jeffery,Dan Ernst.Mibench:A free,commercially representative embedded benchmark suite.In:Proc.IEEE 4th Annual Workshop on Workload Characterization.Los Alamitos,CA:IEEE Computer Society Press,2001
  • 9Henk Corporaal.Microprocessor Architecture from VLIW to TTA.New York:John Wiley & Sons Ltd,1998
  • 10D.A.Patterson,J.L.Hennessy.Computer Architecture:A Quantitative Approach.3rd ed.San Francisco:Morgan Kaufman,2002

共引文献8

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部