摘要
合理的Cache预取能有效减少流水线的等待延时,提高CPU性能。文章提出了一种针对ICache的预取算法,把非条件转移指令预取和下一行预取存入预取Buffer,只有失效指令才存入ICache,有效提高了ICache的存储空间利用率,降低同一路径再次失效。
A reasonable cache prefetching can reduce assembly line stop effectively, so it will enhance CPU performance. In this paper, we describe a prefetching algorithm for ICache. it stores uncondition and Next-line prefetched instructions in the prefetcb Buffer, and only missed instructions store in ICache. ln this way it makes the store more effectively, and can avoid instruction missing in the same path next time.
出处
《大众科技》
2011年第11期75-76,共2页
Popular Science & Technology
关键词
高速缓存
指令预取
失效指令
Cache Instructiong Pre-fetehing Missed instruction