高精度CMOS峰值保持电路设计

A High-Precision CMOS Peak Detect and Hold Circuit

介绍了一种CMOS峰值保持电路。该电路具有精度高,输出摆幅大,驱动能力强等特点。电路具有两种工作状态:"读"状态和"写"状态。在"写"状态时,通过OTA追踪信号,将输入信号峰值存储到保持电容中。在"读"状态时,将OTA连接成单位增益放大器使用,将存储在保持电容上电压值读出。该工作过程可以有效消除放大器自身offset产生的影响,减小误差。通过仿真,该电路在输出幅度在400 mV～1.8V范围内,误差小于1%。本电路采用Chartered 0.35μm工艺。

It describes a high-precision CMOS peak detect and hold circuit.The circuit has characteristics of high precision,wide output voltage range and high driving capability.There are two working phases,write phase and read phase.In write phase,the amplifier tracks the input signal,and when the input starts to fall,it puts the peak voltage into a capacitor.In read phase,it turns the amp into a unitygain buffer,and then reads out the peak voltage.The offset error of the amplifier does not contribute to the linearity.Simulation results show the error is less than 1% in the output voltage range from 400 mV to 1.8 V.The circuit will be taped out using the chartered 0.35 μm CMOS process.