一种染色体编码新方法的硬件进化

Hardware evolution based on a new chromosome encoding method

提出了基于FPLA的染色体编码及在此基础上的并行硬件进化方法.该编码方式以与或非门为基本单元,进化时将电路编码染色体按逻辑门分解,进行适应度计算时采用分解逆过程使染色体合并,可以有效缩短进化时间,有利于大规模复杂电路的进化.以4位二进制码转换为格雷码的电路为例进行试验,该方法在20次实验中平均速度提高了32.25%.为实现内进化编写了由染色体生成Verilog硬件语言的C程序,该编码方式同时适用于多输入多输出电路进化且染色体长度可变,利用此特性生成了异构电路,完成了容错,对于实现故障模块在线修复,提高太空恶劣环境中电子系统可靠性具有一定意义.

This paper proposed an FPLA-based chromosome encoding approach and a parallel hardware evolution method on the basis of a new encoding approach. The AND-OR-NOT gates are the basic units of the chromosome, so by decomposing the chromosome while evolving and integrating it when computing the adaptation, the evolution time can be shortened. This benefits the evolution of massive and complex circuits. Taking the circuit of changing 4 bits binary code to gray code as an example, the result shows that the average speed increases 32.25 percent over 20 evolutions when using the proposed method. In order to facilitate intrinsic evolutions, the C program was also exploited for translating the chromosome to Verilog hardware language. The encoding method was able to handle multi-input and multi-output circuit evolution, and the chromosome＇ s length was variable. According to the evolution of the heterogeneous circuits based on this feature, fault tolerance was achieved. This work is significant for online repair used to improve the reliability of electronic systems exposed to harsh space environments.