2Inyeol Lee, Changsik Yoo, Wonchan Kim, et al. A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array[C].In:42^nd ISSCC ,Proceedings of the International Solid-State Circuits Conference, 1996, San Francisco USA:IEEE Press, 1996:198-199.
3Ching-Che Chung, Chen-Yi Lee. An All-Digital Phase-Locked Loop for High-Speed Clock Generation[J]. IEEE Journal of Solid-state Circuits, February 2003,38(02):347-351.