锁相环系统中的VCO的分析与设计

Design and Analysis of VCO in PLL system

研究了一种用于锁相环(PLL)的宽带低噪声的压控振荡器(VCO),采用了谐波滤除电阻技术和源级带反馈电阻技术降低噪声和功耗,设计使用了一种新型的变容管拓扑结构(back-to-back varactor)改善压控增益的线性范围,抑制了输出电压幅度对相位噪声的影响。采用chartered 0.35um CMOS工艺在Mentor Graphics Eldo-RF环境下进行仿真,结果表明振荡器在1mA工作电流下,在2.4GHZ达到-119.5dBc/Hz@1NHz的相位噪声,功耗为3.0mw。

A wide-bandwidth,low-noise VCO used in PLL system was investigated,including a harmonic filtering resistor and source damping resistors to reduce the phase noise and power dissipation.The back-to-back varactor topology is identified as a suitable solution to linearize the tank capacitance.The amplitude to phase noise conversion is greatly attenuated.The circuit was simulated using 0.3Sum CMOS technology in Mentor Graphics Eldo-RF environment,the simulation results show that the phase noise of the oscillator can reach -119.5dBc/Hz@1MHz,at 2.3GHz,1mA,the power dissipation is only 3.0 mw.