基于IP核的FIR滤波器在新型FPGA的实现

The Design of IP Core Based FIR Filter and Implement in New FPGA

介绍了的新型FPGA芯片Stratix系列EP1S40的特点及其编程与配置。通过IP核的重用和外围电路的VHDL设计,实现了基于FIR滤波的数字正交变换。

The feature of Stratix family device EP1S40 of Altera Co.and its configuration is presented.The digital downconverter is designed by reusing IP core.and implemented successfully in FPGA devices.