基于FPGA的高分辨率全帧CCD驱动电路设计

Design of FPGA-based High-resolution Full-frame CCD Driving Circuit

针对1100万像素(4008×2672)全帧CCD芯片FTF4027M的驱动时序要求,介绍了基于现场可编程门阵列(FPGA)来设计产生该芯片的复杂驱动时序以及其它控制逻辑时序的方法。给出了FPGA实现电路组成和逻辑仿真波形,通过对电路的输出波形的测试结果表明,该方法是可行的。

According to the driving timing of 11M(4008×2672)full-frame CCD image sensor FTF4027M.a design meth- od based on FPGA is introduced for the complex driving timer and for the other control logical timer.The circuit of FP- GA and the waveform of logical simulation were introduced in details.The output waveform is the same figure as the simulation waveform.This result indicates that the design method is feasible.