基于CPLD的高速可重构PCM帧同步器的实现

Realization of High-speed Reconfigurable Frame-synchronizer Based on CPLD

给出一种基于 CPL D的高速可重构帧同步器的设计思路和实现方法 ,探讨如何提高系统速度及其可靠性。既采用数字化相关检测技术和可容错的校验保护技术 ,又采用系统内在线可编程 ISP(In- System Programm ing)技术和提高系统速度的流水线技术 ,综合高速 PCI总线接口设计 。

A design idea and realization of the high speed reconfigurable frame synchronizer based on CPLD is presented. How to improve the system speed and reliability is also discussed.We adopt many techniques during the design,including digital interrelated checkup,error tolerable checkout and protection,in system programming.We also use pipeline to improve system speed. Integrating high speed PCI bus interface design,we realize the on line reconfiguration of high speed frame synchronizer.