可重构的通用硬线逻辑电路算法验证平台的设计

The Design of an Universal Verification Platform for Reconfigurable Hardwired Logic of Algorithm

介绍一种通用硬线逻辑算法验证平台的设计思路。在人机交互界面干预下,可通过高性能的PCI局部总线接口,从文件系统向算法验证平台系统分别传送构成待验证算法硬线逻辑的码流以及该算法运算所需的输入数据,并将该算法的运算结果向文件系统输出。利用这个平台,已验证基于小波变换和零树编码的先进的图像压缩/解压缩算法的硬线逻辑。本系统的框架也可用于验证其它用同类且规模类似的FPGA(CPLD)实现的硬线逻辑算法。因此。

In this paper,an advanced verification platform for reconfigurable hardwired logic of universal algorithm is introduced.Under the control of interactive interface,through PCI Bus,the bit stream data for hardwired logic reconfiguration of algorithm and the data for computing can be download form file system to the platform subsystem,and the result data of computing can be upload to file system.On the subsystem,the hardwired logic of the advanced algorithm based on Zero Wavelet Tree for image compression/decompression is verified.Moreover,the framework can be used as an universal platform to verify any other hardwired logic algorithm that can be implemented on FPGA.