摘要
This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.
This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.
出处
《湖南大学学报（自然科学版）》
EI
CAS
CSCD
2000年第S2期61-77,共17页
Journal of Hunan University:Natural Sciences
