基于事件驱动的数字逻辑功能仿真工具

Event-Drive Digital Logic Simulation Tool

本文介绍了现代专用集成电路(ASIC)芯片的设计流程、详细讨论了对Verilog HDL所描述的数字电路网表进行逻辑功能仿真工具LGS的开发过程.主要包括分层建模、事件驱动算法和具体实现中的一些技术问题.也论述了面向对象技术及C++在EDA(Electronic Design Automation)工具开发中的应用.最后给出一个LGS应用于乘法器电路设计的仿真验证示例.

This paper introduces the modern design circle of ASIC chip. A method of developing LGS, which is a logical simulation tool using C++ and the event-driven algorithm, is discussed in detail. The LGS is used on the n'etlist of digital circuit, which is described by Verilog HDL. A design can be envisioned as a hierarchical composition of modules. The paper describes the event-drive algorithm and some technical field when implemented. It also introduces the application of object orient technology in developing EDA (Electronic Design Automation) tools. At the end of the paper, an example of LGS simulation verification on a multiplier circuit design is given.