有限间距误差限算法硬件实现电路中的关键控制电路的设计

Key Controlling Circuit Design of Hardware Realization Circuit of Data Compression Algorithm with the Limited Error and Fixed Step

存储测试系统压缩电路是一种动态自适应压缩电路,它能够实现对250kHz以上快速信号的冗余判断、压缩编码及存储控制。本文主要对电路总体设计过程中的几个关键控制部分即:冗余采样点预测期间数据传输流向控制电路、冗余点数计数器的清零电路、冗余点采样传输期间地址非匀速推进控制电路的设计及其功能的实现加以详细的阐述。

Storage test system comprssion realization circuit is a kind of dynamic self-adaptive compression circuit. It can carry out such function as redundancy identification of the high variable speed signal with the frequency over 250kH/,, The paper mainly describes several key controlling unit's design in detail among the general circuit design.The key controlling unit described in the paper includes the data transmission direction controlling circuit during the period of redundancy sampling prediction, the redundancy counter's /ero clearing circuit and the non-uniform speed controlling circuit of address generation during the redundancy sampling data trasmission period.