数据采集系统中SRAM的误码机理分析

SRAM ERROR CODE MECHANISM ANALYSIS FOR DATAACQUISITION SYSTEM

在采用SRAM作为数据存储器的数据采集系统中,由于对存储器操作时序或SRAM本身工作机理的原因,在电源通断电的过渡过程中常会出现存储器中数据被改写的现象,本文将就这一现象从电路设计、电路状态时序设计等方面进行分析研究,特别对数据改写率与外接交流稳压电源中的确直流输出电容的关系,从试验的基础出发进行了深入的研究,并得到了结论。最后针对这一现象在电路设计、状态时序设计等各方面提出了解决措施,保证采集数据的可信度与可靠度。

In the data acquisition system which adopted the SRAM, memorized data rewritten often occurs in the procedure of powering transition due to the memory operation time sequence and the SRAM mechanism. This paper analyzes the circuit design and the circuit state timing diagram, and has erived the conclusion. According to the conclusion, the paper puts forward the measures in circuit designing and the state designing to eliminate the error coding phenomenon in order to improve the circuit confidence and reliability.