摘要
Programmable logic array (PLA) is a popular structure for realizing arbitrary combinational networks. Easy test generation (ETG) PLA, a kind of PLA design with the property of easy test generation, is s PLA design with added product terms and/or outputs such that tests are easy to generate, even no effort on test generation and fault simulation is necessary. This paper attempts to further clarify the concept of ETG circuits and extends the concepts of pseudo-nonconcurrency and separation to reduce the hardware overhead, based on a unified singlefault model. Experimental results show that the hardware overhead is generally less than 5%, which is considered to be the lowest cost for testable PLA designs.
Programmable logic array (PLA) is a popular structure for realizing arbitrary combinational networks. Easy test generation (ETG) PLA, a kind of PLA design with the property of easy test generation, is s PLA design with added product terms and/or outputs such that tests are easy to generate, even no effort on test generation and fault simulation is necessary. This paper attempts to further clarify the concept of ETG circuits and extends the concepts of pseudo-nonconcurrency and separation to reduce the hardware overhead, based on a unified singlefault model. Experimental results show that the hardware overhead is generally less than 5%, which is considered to be the lowest cost for testable PLA designs.
基金
Project supported by the National Natural Science Foundation of China, and subsidized by K. C. Edu cation Foundation.
