电路可接受域窗函数及样本点一阶矩轨迹

Circuit Acceptability Region Window Function and Sampling Point One-order Moment Locus

本文由大样本抽样效应,提出了电路可接受域的正态窗模型,导出了电路指标约束在元件参数空间映射的正态窗函数;提出了一阶矩轨迹的概念,并由此导出了中心值设计的叠代方程。与国外有关文献比较,本文导出的方法可使设计改善,并节省机时。

By the effect of circuit acceptability region larger sampling, in this paper, a Gausian Window model of circuit performance restraint mapping in element parameter space is proposed. Through rigorous mathematic deduction, a reduction window function is calculated, and a concept of one-order moment locus advocated. And herefrom, a centering design iteration equation is deduced. Comparing with foreign doeuments, the method based on this theory can improve design results and save computer CPU time.