摘要
利用现场可编程门阵列(FPGA,Field Programmable Gate Array)实现了一种基于深空通信的级联码结构。该级联码包括内码和外码,内码是基于全并行的软判决Viterbi译码器结构,用来纠正随机错误,结合帧同步技术完成解交织,然后进行外码里德-所罗门码(RS codes,Reed-solomon codes)译码,纠正突发错误,实现级联码译码。通过实际硬件测试,在满足系统误码率要求的前提下,使用该级联码译码器能够降低发射功率或减少天线尺寸,对降低系统成本及提高系统性能具有非常重要的作用。
The concatenation decoding based on deep-space communication is designed and implemented,which is composed of inner decoding and outer decoding,inner decoding is Viterbi decoding and is used to correct random error with the structure of all parallel ACS and soft-decision.Interleave technique comes true after frame synchronization is realized.Then RS decoding is designed to correct burst errors.Finally an actual test on the program by hardware is done,and the result indicates that the concatenation decoding could effectively reduce transmission power or the antenna size,and thus could play important role in reducing system cost and improving system performance.
出处
《通信技术》
2011年第11期32-34,共3页
Communications Technology