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一种应用于流水线ADC采样保持电路的设计

Design of Sample-and-hold Circuit for a Pipeline ADC
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摘要 介绍了一种应用于12位、10MS/s流水线模数转换器前端的高性能采样保持(SH)电路的设计。该电路采用全差分电容翻转型结构及下极板采样技术,有效地减少噪声、功耗及电荷注入误差。采用一种改进的栅源电压恒定的自举开关,极大地减小电路的非线性失真。运算放大器为增益增强型折叠式共源共栅结构,能得到较高的带宽和直流增益。该采样保持电路采用JAZZ 0.6μm BiCMOS工艺来实现,在5V电源电压、10MHz采样频率下,当输入信号频率为1MHz时,仿真结果显示无杂散动态范围(SFDR)为107.82dB、信噪比(SNR)为87.8dB、总谐波失真比(THD)为-105.2dB。该部分电路版图面积为0.4mm×0.8mm,功耗仅为11mW。 A high performance sample and hold（SH） circuit for use in the front end of a 12-bit 10MS/s Pipeline ADC is presented.The full differential capacitor flip-around architecture has been used to reduce both noise and power.To reduce the nonlinearity error cause by the sampling switch,a signal dependent clock bootstrapping system is used.A fully differential folded cascade operational amplifier is designed using a gain-boosted circuit to get high gain and wideband.It is implemented using 0.6μm BiCMOS process,and simulation results demonstrate that the S/H circuit consumes 11mW at 5V supply with a sampling rate of 10MHz.A 107.8dB spurious-free dynamic range（SFDR）,an 88.1dB signal and noise ratio（SNR）,and a-105.2dB total harmonic distortion（THD）are obtained.
作者 周佳宁 李荣宽
机构地区 电子科技大学电工学院
出处 《电子与封装》 2011年第11期18-21,32,共5页 Electronics & Packaging
关键词 流水线ADC 栅压自举开关 增益增强型运算放大器 采样保持电路 pipeline ADC bootstrapped switch gain-boosted operational amplifier sample-and-hold circuit
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献10

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二级参考文献10

  • 1Iroaga E,Murmann B. A 12-bit 75MS/s pipelined ADC using incomplete settling. IEEE J Solid-State Circuits, 2007,42 (4) : 748
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电子与封装
2011年 第11期

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