LDLT分解协处理器的并行结构研究

Research on Parallel Architecture for LDLT Decomposition Co-processor

为提高LDLT分解协处理器的性能,基于FPGA平台,研究其并行结构。分析循环片间的数据依赖关系,提出LDLT分解细粒度并行算法,并在可扩展一维阵列处理器中加以实现,利用主机、算法加速器组成单精度浮点LDLT分解协处理器的并行结构。实验结果表明,与运行在2.50 GHz Pentium微处理器上的C代码相比,该协处理器可获得32.03倍~43.25倍的性能提升。

This paper studies parallel architecture and implementation for large-scale symmetric matrix LDLT decomposition co-processor which based on Field Programmable Gate Array（FPGA） platform to enhance the performance of it.It proposes a fine-grained parallel algorithm basing the data dependency analysis.Then a scalable LDLT decomposition array processor is presented to implement this algorithm.Main engine and arithmetic accelerator constitute the parallel architecture of a single precision floating-point LDLT decomposition co-processor.Experimental results show that,a maximum factor of 43.25 and 32.03 in average speedup can be achieved compare to 2.50 GHz Pentium CPU with C program.