高速可配置RS纠删解码器的VLSI设计

VLSI Design of High-speed Reconfigurable Reed-Solomon Error-and-erasure Decoder

目前对可配置纠错与删除(纠删)解码器研究较少。为此,采用性能优异的RS编码方法,提出一种高速可配置RS纠删解码器的超大规模集成电路(VLSI)架构,并详述可配置纠删BM模块的构成。该架构通过折叠技术,使解码器在保证高速的前提下降低硬件复杂度。通过0.18μm工艺和Design Complier工具综合测试结果表明,与同类解码器研究相比,该解码器在硬件复杂度吞吐率和可配置性方面,均具有较大优势。

Aiming at the problem that he research and application on reconfigurable error-and-erasure decoders remains limited.This paper presents a Very Large Scale Integration（VLSI） architecture for high-speed reconfigurable error-and-erasure Reed-Solomon（RS） decoder.In digital transmission procedure,RS codes are widely employed due to the excellent error/erasure correction capability.Based on the ultra-folded technology,the proposed architecture achieves not only high speed but also low hardware complexity.Through 0.18 μm technology and design complier tool,the results show that it is a competitive candidate in hardware complexity,throughput and reconfiguration.