用于成品率分析芯片的LVS方法

LVS Method for Yield Analysis Chip

研究成品率分析芯片的特点和设计流程,提出适用的LVS方法。该方法结合传统的LVS及形式验证,能够解决成品率分析芯片中违反设计规则、版图和电路图不匹配等特殊结构的验证问题。将该方法与传统验证流程相融合,用于成品率分析芯片的设计和验证。实验结果证明,成品率分析芯片验证流程具有正确性和稳定性。

The characters and design flow of yield analysis chip are studied.Yield analysis chip contains special components with violation of design rules and mismatch of layout and schematic,so a new method is presented which is the combination of traditional Layout Versus Schematic（LVS） method and formal verification.Yield analysis chip is designed and verified under the new flow.Experimental result shows that the verification process of yield analysis chip is right and stable.