摘要
A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed. The trequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals. Compared with conventional dividers, the circuit achieves an output 1/Q phase sequence that is independent of the input I/Q phase sequence. Moreover, the third harmonic is effectively suppressed by employing a double degeneration technique. The design is fabricated in TSMC 0.13-#m CMOS and operated at 1.2 V. While locked at 8.5 GHz, the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of-124 dBc/Hz at a 10 MHz offset. The circuit achieves a locking range of 15% while consuming a total current of 4.5 mA.
A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed. The trequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals. Compared with conventional dividers, the circuit achieves an output 1/Q phase sequence that is independent of the input I/Q phase sequence. Moreover, the third harmonic is effectively suppressed by employing a double degeneration technique. The design is fabricated in TSMC 0.13-#m CMOS and operated at 1.2 V. While locked at 8.5 GHz, the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of-124 dBc/Hz at a 10 MHz offset. The circuit achieves a locking range of 15% while consuming a total current of 4.5 mA.
基金
Project supported by the National Sci&Tech Major Projects of China(Nos.2009ZX03006-007-01,2009ZX03007-001,2009ZX03006- 009)
the National High Tech R&D Program of China(No.2009AA01Z261)
