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12.5 Gbps 1:16 DEMUX IC with high speed synchronizing circuits 被引量：1

12.5 Gbps 1:16 DEMUX IC with high speed synchronizing circuits
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摘要 A 12.5 Gbps 1：16 demultiplexer （DEMUX） integrated circuit is presented for multi-channel high-speed data transmission. A novel high-speed synchronizing technique is proposed and integrated in this DEMUX chip. Compared with conventional synchronizing techniques, the proposed method largely simplifies the system config- uration. The experimental result demonstrates that the proposed circuit is effective in two-channel synchronization under a clock frequency of 12.5 GHz. The circuit is realized using 1 μm GaAs heterojunction bipolar transistor technology with die area of 2.3 ×2.3 mm^2. A 12.5 Gbps 1：16 demultiplexer （DEMUX） integrated circuit is presented for multi-channel high-speed data transmission. A novel high-speed synchronizing technique is proposed and integrated in this DEMUX chip. Compared with conventional synchronizing techniques, the proposed method largely simplifies the system config- uration. The experimental result demonstrates that the proposed circuit is effective in two-channel synchronization under a clock frequency of 12.5 GHz. The circuit is realized using 1 μm GaAs heterojunction bipolar transistor technology with die area of 2.3 ×2.3 mm^2.
作者 周磊 吴旦昱 陈建武 金智 刘新宇
机构地区 Institute of Microelectronics Key Laboratory of Microelectronics Devices & Integrated Technology
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第12期144-148,共5页 半导体学报（英文版）
基金 Project supported by the State Key Development Program for Basic Research of China(No.2010CB327505)
关键词 DEMULTIPLEXER SYNCHRONIZATION heterojunction bipolar transistor demultiplexer synchronization heterojunction bipolar transistor
分类号 TN43 [电子电信—微电子学与固体电子学]
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参考文献11

  • 1Tanaka K, Shikata M, Kimura T, et al. High speed 8: 1 multiplexer and 1:8 demultiplexer ICs using GaAs DCFL circuit. 13th Annual Gallium Arsenide Integrated Circuit Symposium Tech Dig, 1991:229.
  • 2Runge K, Zampardi P J, Pierson R L, et al. High speed Al- GaAs/GaAs HBT circuits for up to 40 Gb/s optical communication. 19th Annual Gallium Arsenide Integrated Circuit Symposium Tech Dig, 1997:211.
  • 3lshii K, Nosaka H, Nakajima H, et al. Low-power 1:16 DEMUX and one-chip CDR with 1:4 DEMUX using InP-InGaAs heterojunction bipolar transistors. IEEE J Solid-State Circuits, 2002, 37(9): 1146.
  • 4Yen J, Case M G, Nielsen S, et al. A fully integrated 43.2 Gb/s clock and data recovery and 1:4 DEMUX IC in InP HBT technology. IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, 2003:240.
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同被引文献12

  • 1Kim, Byung-Guk,Kim, Lee-Sup,Byun, Sangjin,Yu, Hyun-Kyu.A 20 Gb/s 1:4 DEMUX without inductors and low-power divide-by-2 circuit in 0.13 μm CMOS technology. IEEE Journal of Solid State Circuits . 2008
  • 2Jooseok LeeJongwon LeeKyounghoon Ya.A Low-Power 40-Gb/s 1:2 Demultiplexer IC Based on a Resonant Tunneling Diode. IEEE Transactions on Nanotechnology . 2012
  • 3Seckin, Utku,Yang, Chih-Kong Yen.A comprehensive delay model for CMOS CML circuits. IEEE Transactions on Circuits and Systems I: Regular Papers . 2008
  • 4Mineyamal A,Suzuki T,Ito H,et al.A 20 Gbit/s 1∶4DEMUX with near-rail-to-rail logic swing in 90 nmCMOS process. Proceedings of 2009 IEEE MTT-SInternational Microwave Workshop Series on Signal In-tegrity and High-Speed Interconnects . 2009
  • 5Xie Feng,Xu Yanyi.Design of low voltage ultra high-speed 1∶16 DEMUX by 0.18μm CMOS process. Proceedings of the 2nd International Conference on Fu-ture Computer and Communication . 2010
  • 6Shuangchao Yan,Yingmei Chen,Tao Wang,Hui Wang."A 40-Gb/s Quarter Rate CDR with 1:4 Demultiplexer in 90-nm CMOS Technology". 12th IEEE International Conference on Communication and Technology (IEEE ICCT 2010) . 2010
  • 7Tanga X S,Wang X J,Zhang S Y,et al.A 2-Gbit/s1∶16 Demultiplexer in 0.18μm CMOS process. Proceedings of 2008 G lobal Symposium on MillimeterWaves . 2008
  • 8Y.J.Li,J.Feng."A 3.6Gb/s 60m W 4:1 multiplexer in 0.35-μm CMOS". Proceedings of International Symposium on Signals,Systems and Electronics . 2010
  • 9C.C.Zhang."Research on ultra high speed clock and data recovery integer circuits and demultiplexer integrated circuits". . 2009
  • 10王贵,王志功,李伟,唐万春.基于锗硅工艺的40-Gb／s分接器[J].固体电子学研究与进展,2009,29(2):276-280. 被引量：2

引证文献1

Journal of Semiconductors
2011年 第12期

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