面向片上网络路由器漏流功耗优化的自适应缓冲管理策略

Adaptive Buffer Management for Leakage Power Optimization in NoC Routers

随着单芯片上集成处理器数量的增加,片上网络逐渐成为多核处理器中非常有前景的互连结构.互连网络成为片上多处理器功耗的重要消耗部件之一.而输入缓冲器是路由器漏流功耗的最大消耗单元,采用门控电源是降低其漏流功耗的有效手段.自适应缓冲管理策略能够根据网络中通信量,自适应地关闭/打开缓冲的一部分,从而降低路由器漏流功耗.而为了减小对网络延迟的影响,该策略中采用的提前唤醒技术能够隐藏缓冲的唤醒延迟.在网络注入率较低情况下,两项缓冲不关闭策略下的网络延迟几乎不受唤醒延迟影响.模拟结果显示,在4×4的二维Mesh中,即使网络注入率为0.7,漏流功耗的节约率依然可以高达46%;网络注入率小于0.4时,两项缓冲不关闭策略下的网络延迟最大仅仅增加了3.8%.

Network on chip （NoC） is becoming a promising design solution for interconnection between processor cores and cache banks in CMP （chip multi-processors） as the number cores on a chip increase. Interconnect network is the main power consumption component in CMP. Input buffer is the largest leakage power consumer in DVOQR （dynamic virtual output queues router）, and it consumes about 64.9% of the total router leakage power. The run time power gating is one of the attractive methods to reduce the leakage power of routers. The fraction of input buffers can be turned on/off to reduce the leakage power of buffers in adaptive buffer management strategy proposed in this paper, according to the traffic in network. The wakeup latency will lead to the average network latency increase. The look-ahead wakeup technology can hide the wakeup latency and decrease the negative effect. The average network latency is not affected by the wakeup latency in the two-entry-buffer-never-turned-off strategy under low offered traffic rate. Simulation results display that the reduction of leakage power consumed by buffers is up to 46% when offered traffic rate is 0.7 and that the increase of average network latency is as much as 3.8% in two-entry-buffer-never-turned-off strategy when the offered traffic rate is less than 0.4.