H.264去块滤波的流水线结构硬件设计与优化

Pipeline Hardware Design and Optimization for H.264 Deblocking Filter

针对H.264去块滤波器实现过程中间数据量大、处理速度不够快的问题,设计了一种优化的基于流水结构的去块滤波结构。该设计中,对去块滤波器的处理顺序和数据通路进行了优化设计,中间数据得到及时处理,减少了存储中间数据的FPGA硬件资源,流水结构也减少了去块滤波的时钟周期,提高了处理速度。硬件逻辑实现的实验结果表明,设计的去块滤波器能够很好地减少视频的块效应,加速处理,节约硬件资源,满足了高清视频的要求。

With respect to the bottlenecks of H. 264 deblocking filter,which involve considerable volume of intermediate data and unagreeable processing speed,an optimization for pipeline-based deblocking filter was proposed. In the course of design for it,the processing sequence and datapath were optimized, then the intermediate data were filtered timely, thereby reducing the hardware resources for storage of them and cutting down the clock cycles for deblocking filter, while advancing the processing speed. Via the experiments of hardware implementation, the results demonstrate that the proposed deblocking filter is able to limit the block effect, accelerate the processing, while meeting the requirement of few hardware resources for high-definition video.