高速低抖动时钟稳定电路设计

Design of high-speed low-jitter clock stabilizer circuit

基于0．18μmCMOSMixedSignal工艺，设计实现了用于高速ADC的低抖动时钟稳定电路。在传统延迟锁相环结构（DLL）时钟电路研究基础上进行改进：设计基于Rs锁存器的新型鉴相器，消除传统鉴相器相位误差积累效应；采用连续时间积分器取代电荷泵进行时钟占空比检测，减小由于电荷泵充放电电流不一致而导致的误差。芯片面积为0．339mm×0．314mm，后仿真结果表明，在20～150MHz宽采样频率范围内，实现10％～90％占空比的输入时钟自动调整至（50±0．15）％，且锁定时间小于100ns，抖动为0．00127ps@150MHz，满足高速高精度ADC时钟性能要求。

Based on 0.18μm CMOS mixed signal process, a high-precise clock stabilizer circuit for high-speed ADC was presented. A double-edge triggered RS latch phase detector was designed to eliminate the effect of the accumulation phase of traditional phase detector. A continuous time integrator was utilized to test the clock duty cycle and control the rising edge of an inverter, which reduced the charge and discharge current inconsistent errors of the charge pump. The chip area is about 0.339 mm×0.314 mm. The post-simulation results show that the circuit can adjust output clock duty cycles to （50±0.15）% with 10%-90% input duty cycle from 20-150 MHz in less than 100 ns, and the measurement jitter is 0.00127 ps at 150 MHz. Therefore it can satisfy the clock requirement of high-performance ADC.