RapidIO应用系统及其验证模型的设计与测试

Design and testing of RapidIO application and verification model

针对传统嵌入式系统中互连通信的问题,提出一种可用于嵌入式系统内部通信的基于RapidIO的应用系统及其验证模型。该方案采用Altera公司的IP核和Cyclone系列FPGA,建立了串行RapidIO(SRIO)接口通信系统,并对其功能进行验证。详细分析了RapidIO应用系统及其验证模型的功能结构和运行原理,为提高嵌入式系统内部模块的通信速率提供了解决方案。

Aiming at the problem existed in the traditional interconnection of embedded system, a scheme of RapidIO application and verification model, which can be used for the communication in the embedded system, is proposed. Based on the IP Core and Cyclone serial FPGA of Ahera Company, this scheme builds communication system of Serial RapidIO （SRIO） whose functions are verified. The structure and operation principle of RapidIO application and verification model are elaborated, which give a solution to the improvement of communication rate in the embedded system.